

// Modify signal hierarchy here
`define PC          tb_core.iaddr
`define STAT        tb_core.stat
`define W_OPCODE     tb_core.U_cpu.U_wrtbak.w_opcode
`define W_STAT      tb_core.U_cpu.U_wrtbak.w_stat
`define CC          tb_core.U_cpu.U_execute.U_regCC.e_cc
`define R0         tb_core.U_cpu.U_decode.U_regFile.r0
`define R1         tb_core.U_cpu.U_decode.U_regFile.r1
`define R2         tb_core.U_cpu.U_decode.U_regFile.r2
`define R3         tb_core.U_cpu.U_decode.U_regFile.r3
`define R4         tb_core.U_cpu.U_decode.U_regFile.r4
`define R5         tb_core.U_cpu.U_decode.U_regFile.r5
`define R6         tb_core.U_cpu.U_decode.U_regFile.r6
`define R7         tb_core.U_cpu.U_decode.U_regFile.r7

`define BMEM0       tb_core.U_mem.bank0.mem[i][7:0]
`define BMEM1       tb_core.U_mem.bank1.mem[i][7:0]
`define BMEM2       tb_core.U_mem.bank2.mem[i][7:0]
`define BMEM3       tb_core.U_mem.bank3.mem[i][7:0]
`define BMEM4       tb_core.U_mem.bank4.mem[i][7:0]
`define BMEM5       tb_core.U_mem.bank5.mem[i][7:0]
`define BMEM6       tb_core.U_mem.bank6.mem[i][7:0]
`define BMEM7       tb_core.U_mem.bank7.mem[i][7:0]
`define BMEMSIZE    tb_core.U_mem.memsize

`define FSTALL      tb_core.U_cpu.F_stall
`define DSTALL      tb_core.U_cpu.D_stall
`define ESTALL      tb_core.U_cpu.E_stall
`define MSTALL      tb_core.U_cpu.M_stall
`define WSTALL      tb_core.U_cpu.W_stall

